SINC filters are well known as decimation filters used in ΔΣ A/D converters. SINC filters can be represented by using a transfer function of (1−z−N)/(1−z−1). The effect of noise shaping is successfully enhanced by increasing the order of a ΔΣ modulator used in ΔΣ A/D converters. However, it is well known that the order of a decimation filter (SINC filter) at the subsequent stage needs to be higher than the order of the ΔΣ modulator.
For example, an A/D converter using a second-order ΔΣ modulator is considered now. A third-order filter is needed as a SINC filter as illustrated in FIG. 7. This SINC filter can be represented by a transfer function of {(1−z−N)/(1−z−1)}^3. It is also well known that integrator units that constitute the denominator part of the transfer function and differentiator units that constitute the numerator part of the transfer function are separated from each other, and the differentiator units are disposed to follow down-sampling at a frequency of 1/N. In the example illustrated in FIG. 7, the SINC filter includes three integrator units 100 connected in cascade, three differentiator units 101 connected in cascade, and a frequency converter unit 102 that connects the cascade of the integrator units 100 and the cascade of the differentiator units 101 to each other. The integrator units 100 operate at a sampling frequency of fS. The differentiator units 101 and the frequency converter unit 102 operate at a sampling frequency of fD=fS/N.
Filters for removing the utility frequency of 50 Hz/60 Hz are often needed in manufacturing-related applications, such as industrial applications. Band-limit filters or notch filters are known as filters that remove a specific frequency, such as 50 Hz/60 Hz. Notch filters can be implemented as digital circuits as illustrated in FIGS. 8 and 9 although these filters can be implemented also as analog circuits.
A notch filter that removes a 50-Hz component contained in input data includes a differentiator unit 200 and an integrator unit 201 as illustrated in FIG. 8. In the example in FIG. 8, the 50-Hz (=20 ms) frequency component is successfully removed from data sampled at a sampling frequency of 100 Hz, that is, data having a period of 10 ms, by connecting in cascade two delay units of the differentiator unit 200 and determining a difference between data of interest and data preceding the data of interest by two samples (see Literature [Shogo NAKAMURA, “Digital Filters for Beginners”, Tokyo Denki University Press, pp. 154-165, 1989]).
A notch filter that removes a 60-Hz component contained in input data includes a differentiator unit 300 and an integrator unit 301 as illustrated in FIG. 9. In the example in FIG. 9, the 60-Hz frequency component is successfully removed from data having a period of 10 ms by connecting in cascade five delay units of the differentiator unit 300 and determining a difference between data of interest and data preceding the data of interest by five samples.
A utility-frequency-removed conversion result is successfully obtained by disposing both or one of the notch filters illustrated in FIGS. 8 and 9 at the subsequent stage of the SINC filter illustrated in FIG. 7 in combination. In countries where both utility frequencies of 50 Hz and 60 Hz are used, such as in Japan, both 50 Hz and 60 Hz need to be successfully removed. Accordingly, a notch filter that removes 50 Hz and a notch filter that removes 60 Hz need to be connected in series as illustrated in FIG. 10. Configurations such as automatically determining whether the utility frequency is 50 Hz or 60 Hz to select the property of the notch filter or the user setting the property of notch filter by using a switch or the like are possible; however, addition of an extra detection circuit or putting an extra load on the user is not preferable.
In the configuration in FIG. 10, since both the integrator units and the differentiator units are configured as digital circuits, the signal line has a width of a plurality of bits. The bit width needs to be selected so as to prevent the occurrence of an internal overflow. The bit width is dependent on a down-sampling frequency ratio N, and a bit width of K×log 2(N)+1 [bit] is needed (see Literature [J. C. Candy and G. C. Temes, “Oversampling Delta-Sigma Data Converters”, IEEE Press, pp. 1-29, 1991]). Here, K denotes the number of stages of the filter. When the SINC filter is a third-order filter as illustrated in FIGS. 7 and 10, K is equal to 3. For example, if an accuracy of 16 bits is desired in the case of N=256, 25 bits are needed. Thus, a register corresponding to such a bit width is necessary.